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通用信道编译码算法物理性能快速仿真系统

274    2024-06-26

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作者:秦明伟, 高永翔, 李陈, 侯宝临, 王焕

作者单位:西南科技大学信息工程学院,四川 绵阳 621010


关键词:信道编译码;物理性能;仿真系统;软硬件协同;加噪信道


摘要:

为实现信道编译码硬件算法物理性能的快速、准确验证,提出一种软硬件协同的通用化信道编译码算法物理性能快速仿真与性能评估系统。PC上位机软件主要实现模拟信源/噪声数据生成、仿真数据后分析、数据/控制指令传输以及与FPGA下位机交互等功能;FPGA下位机通过设计数据调度与系统控制、信道编译码算法架构、加噪信道以及数据统计等单元,构建通用编译码算法验证系统硬件系统架构,支持不同信道编译码算法物理性能的高效、准确验证。以系统当前支持的BCH码、LDPC码、删余卷积码、RS码及其串行级联码的性能仿真为例开展性能测试,性能恶化最大值低于0.4 dB,在10–7误码率统计量级下,仿真时间低于12 s,验证仿真评估系统的准确性、可靠性与有效性。系统采用的通用级联架构还可支持其他信道编译码算法的快速移植与部署,可为信道编译码算法物理性能快速验证提供一种有效的解决方案。


Fast simulation system for physical performance of universal channel codecs
QIN Mingwei, GAO Yongxiang, LI Chen, HOU Baolin, WANG Huan
School of Information Engineering, Southwest University of Science and Technology, Mianyang 621010, China
Abstract: In order to realize fast and accurate verification of physical performance of hardware implementation algorithm of channel coding and decoding, the paper proposed and designed a universal system with software- hardware collaboration for fast simulation and evaluation of physical performance of channel coding and decoding algorithm. The PC mainly realized the generation of analog source data and noise data, data analyzing after simulation, command transmission of data or control as well as interacting with FPGA. The hardware system architecture of the universal algorithm verification system was constructed in this paper through designing the mechanism of data scheduling and system control, architecture of channel coding and decoding algorithm as well as the unit of noise adding channel and data statistics in FPGA, leading to supporting efficient and accurate verification of physical performance of different channel coding and decoding algorithms. The performance test is carried out by taking the performance simulation of BCH code, LDPC code, punctured convolutional code, RS code and its serial concatenated code currently supported by the system as an example, the maximum performance degradation is lower than 0.4 dB, under the statistical magnitude of 10–7 bit error rate, the simulation time is less than 12 seconds, which verified the accuracy, reliability and effectiveness of the simulation and evaluation system. The universal cascading architecture adopted by the system can also support the rapid migration and deployment of other channel coding and decoding algorithms, providing an effective solution for the rapid verification of the physical performance of channel coding and decoding algorithms.
Keywords: channel coding and decoding; physical performance; simulation system; software-hardware collaboration; noise adding channel
2024, 50(6):98-105 收稿日期: 2022-07-26;收到修改稿日期: 2022-09-15
基金项目: 国家自然科学基金(62261051);四川省科技厅应用基础面上项目(2019YJ0309)
作者简介: 秦明伟(1979-),男,河南陕县人,教授,博士,研究方向为软件无线电与集群认知通信、高速信号采集与实时处理、硬件加速与自适应计算。
参考文献
[1] 陈曦原. 信道编码技术在卫星通信中的重要应用研究[J]. 数字通信世界, 2019, 2(2): 172-175.
CHEN X Y. Research on the important application of channel coding technology in satellite communication[J]. Digital Communication World, 2019, 2(2): 172-175.
[2] 路文娟, 张辉, 张世强. 无线传感器网络节点通信与定位综合信号设计[J/OL]. 中国测试: 1-6[2022-09-16]. http://kns.cnki.net/kcms/detail/51.1714.TB.20211202.1752.004.html.
LU W J, ZHANG H, ZHANG S Q. Integrated signal design for communication and positioning of wireless sensor network nodes[J/OL]. China Measurement & Test: 1-6[2022-09-16]. http://kns.cnki.net/kcms/detail/51.1714.TB.20211202.1752.004.html.
[3] 富璇, 杨毅, 何思远, 等. 基于Matlab的现代通信系统的仿真应用[J]. 沈阳工程学院学报(自然科学版), 2007(4): 367-370.
FU X, YANG Y, HE S Y, et al. Simulation application of modern communication system based on Matlab[J]. Journal of Shenyang Institute of Engineering(Natural Science), 2007(4): 367-370.
[4] 尚启星. RS码在通信中的性能分析与仿真[J]. 软件导刊, 2014, 13(11): 37-38.
SHANG Q X. Performance analysis and simulation of RS code in communication[J]. Software Guide, 2014, 13(11): 37-38.
[5] 鲁芳旭, 刘翠海. RS码的性能分析与仿真[J]. 数字技术与应用, 2020, 38(8): 25-27.
LU F X, LIU C H. Performance analysis and simulation of RS code[J]. Digital Technology & Application, 2020, 38(8): 25-27.
[6] 詹平红, 李红星, 尹爱兵. LDPC编译码算法的仿真分析[J]. 计算机与数字工程, 2019, 47(5): 5.
ZHAN P H, LI H X, YIN A B. Simulation analysis of LDPC codec algorithm[J]. Computer & Digital Engineering, 2019, 47(5): 5.
[7] 曲国伟, 宋晓萍. 低密度奇偶校验码的混合译码算法[J]. 系统仿真学报, 2018, 30(10): 4009-4013.
QU G W, SONG X P. Hybrid decoding algorithm for low-density parity check codes[J]. Journal of System Simulation, 2018, 30(10): 4009-4013.
[8] 吴博. 基于DVB-S2标准的LDPC并行译码算法研究与GPU实现[D]. 成都: 西南交通大学, 2019.
WU B. Research on LDPC parallel decoding algorithm based on DVB-S2 standard and GPU implementation[D]. Chengdu: Southwest Jiaotong University, 2019.
[9] 夏阁淞, 葛万成. 极化码译码算法的改进与FPGA实现[J]. 通信技术, 2019, 52(11): 2611-2616.
XIA S G, GE W C. Improvement of polar code decoding algorithm and FPGA implementation[J]. Communications Technology, 2019, 52(11): 2611-2616.
[10] 刘梦欣. 基于FPGA的RS编译码研究与设计[D]. 太原: 中北大学, 2020.
LIU M X. Research and design of RS codec based on FPGA[D]. Taiyuan: North University of China, 2020.
[11] MIZUOCHI T, KONISHI Y, MIYATA Y, et al. Experimental demonstration of concatenated ldpc and rs codes by fpgas emulation[J]. IEEE Photonics Technology Letters, 2009, 21(18): 1302-1304.
[12] 宿凌超, 雷茂, 秦明伟, 等. 基于半实物仿真的信道编译码性能验证系统[J]. 制造业自动化, 2022, 44(4): 62-65.
SU L C, LEI M, QIN M W, et al. Channel decoding performance verification system based on hardware-in-the-loop simulation[J]. Manufacturing Automation, 2022, 44(4): 62-65.
[13] 邓莉. 信道编解码算法性能快速验证系统设计[D]. 绵阳: 西南科技大学, 2020.
DENG L. Design of system for rapid verification of channel codec algorithm performance[D]. Mianyang: Southwest University of Science and Technology, 2020.