作者:王建洪1, 王贵柱2
作者单位:1. 四川大学电子信息学院, 四川成都 610064;
2. 河南公安高等专科学校, 河南郑州 450002
关键词:非2次幂; SRLU; VHDL
摘要:
本文提出了一种对非2次幂求余的SRLU算法,并基于该算法出了具体的设计和实现方案,测试表明该方法具有良好的稳定性和快速的收敛性。
Design analysis and implementation of SRLU algorithm
WANG Jian-hong1, WANG Gui-zhu2
1. College of Electronics and Information, Sichuan University, Chengdu 610064, China;
2. Henan Police Technological Academy, Zhengzhou 450002, China
Abstract: This paper provides a new SRLU algorithm for the computation of the remainder of the non-2-power number.The detailed design analysis and implementation scheme of the SRLU algorithm are presented.The algorithm is testified with good stability and fast converge rate.
Keywords: Non-2-power; SRLU; VHDL
2005, 31(2): 88-90 收稿日期: 2004-9-6;收到修改稿日期: 2004-11-12
基金项目:
作者简介:
参考文献
[1] Xilinx, Virtex-II Platform FPGA User Guide, 2002, 12.
[2] Xilinx, Virtex-II Platform FPGA Datasheet, 2002,12.
[3] 卢毅, 赖杰.VHDL与数字电路设计[M]. 北京:科学出版社, 2001, 4.