作者：王涛^1,2, 张德源¹, 郭建军²

作者单位：1. 电子科技大学自动化工程学院, 四川成都 610054;
2. 中国电子科技集团第二十九研究所国家重点研究室, 四川成都 610036

关键词：CompactPCI/PCI总线; DMA; FIFO

摘要：

CompactPCI/PCI总线是一种高速的,独立于CPU的总线结构,其本地总线接口逻辑的设计是应用CompactPCI/PCI总线开发高性能数字通信产品的难点所在。本文通过基于CompactPCI/PCI总线的高速数字IO的设计,详细分析了PCI9054本地总线接口控制逻辑,给出了接口电路的实现结构,并给出了最终的设计方案。

A design of high speed digital IO based on CompactPCI bus

WANG Tao^1,2, ZHANG De-yuan¹, GUO Jian-jiu²

1. School of Automatic Engineering, University of Electronic Science and Technology, Chengdu 610054, China;
2. National EW Lab, The 29 Institute of CETC, Chengdu 610036, China

Abstract: CompactPCI/PCI bus is a kind of bus architecture of high speed and independence of CPU. To utilize CompactPCI/PCI bus to develop digital communication manufactures of high performance, it is important to design the CompactPCI/PCI Card' s local bus interface logic intensively. In this paper, through the design of high speed figure IO based-on CompactPCI/PCI bus, and elaborately analyzing interface control logic of PCI9054' s local bus, figures out the implemented construction of the interface circuits with CPLD, as well the finished design.

Keywords: CompactPCI/PCI bus; DMA; FIFO

2005, 31(6): 110-112  收稿日期: 2004-9-8;收到修改稿日期: 2004-11-20

基金项目: 

作者简介: 

参考文献

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