作者：潘小冬¹, 陈泽祥¹, 黄自力², 高升久²

作者单位：1. 电子科技大学光电信息学院, 四川成都 610054;
2. 西南技术物理研究所, 四川成都 610041

关键词：I²C总线; FPGA; 有限状态机(FSM); Verilog HDL; 初始化

摘要：

以I2C总线协议为根据,用有限状态机(FSM:Finite State Machine)设计了基于FPGA的I2C初始化程序模块。主要内容包括简述I2C总线的特点;介绍用FPGA中FSM开发I2C总线模块时的设计思想和实现过程;给出并解释了部分用Verilog HDL描述I2C总线初始化SAA7111和SAA7121的程序,最后在QuartusII中进行了I2C总线主从模式下的时序仿真和用其内嵌逻辑软分析仪SignalTapII完成了硬件调试。

Design of FSM simulation for I²C bus based on FPGA

PAN Xiao-dong¹, CHEN Ze-xiang¹, HUANG Zi-li², GAO Sheng-jiu²

1. School of Photo-electronic Information, University of Electronic Science and Technology, Chengdu 610054, China;
2. Institute of Southwest Technology and Physics, Chengdu 610054, China

Abstract: According to I²C bus communication protocol,this paper introduced design of the I²C bus by FSM based on FPGA. It mainly includes the brief introduction of the characteristic of I²C bus, the design ideas and implementation process for I²C bus based on FPGA. Then it share and explanation some program of initialization for SAA7111 and SAA7121 in Verilog HDL. Finally timing simulation under master-slave in QuartusII was done, and debugging by SignalTapII on hardware was completed successfully.

Keywords: I²C bus; FPGA; FSM; Verilog HDL; initialization

2007, 33(1): 105-107  收稿日期: 2006-7-26;收到修改稿日期: 2006-9-23

基金项目: 

作者简介: 

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