作者：朱耀辉1,2, 袁晓伟1,2, 郑旭强1,2, 武锦1,2
作者单位：1. 中国科学院微电子研究所，北京 100029;
2. 中国科学院大学，北京 100049
关键词：微电子学与固体电子学;锁相环;分频器;相位噪声
摘要：
为给超高速数模转换器提供稳定的时钟信号，该文基于TSMC 40 nm CMOS工艺设计一款宽带低噪声的锁相环芯片。该芯片设计由二分频和计数器构成的分频器电路，减小吞脉冲带来的时钟抖动，从而优化噪声性能；此外，设计3位差分开关电容阵列，实现宽范围调谐的同时确保相邻调谐区间互相重叠，从而避免工艺误差导致的调谐盲区；最后还设计三阶环路滤波器及改进型差分电荷泵的电路。仿真结果表明，该锁相环具有19.6~27.8 GHz的宽带调谐范围，整体功耗为30 mW，输出频率频偏1 MHz处的相位噪声为–95.6 dBc/Hz。与其他文献的锁相环对比，在其他指标相当的前提下，该锁相环在调谐范围上具有先进性，可作为高性能的时钟信号。
Design of broadband low noise phase locked loop with 19.6-27.8 GHz
ZHU Yaohui1,2, YUAN Xiaowei1,2, ZHENG Xuqiang1,2, WU Jin1,2
1. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;
2. University of Chinese Academy of Sciences, Beijing 100049, China
Abstract: In order to provide a stable clock signal for the ultra-high-speed digital-to-analog converter, this paper designs a broadband low-noise phase-locked loop chip based on the TSMC 40 nm CMOS process. The chip has designed a frequency divider circuit composed of a frequency divider and a counter to reduce clock jitter caused by swallowing pulses, thereby optimizing noise performance; In addition, a 3-bit differential switched capacitor array is designed to achieve wide-range tuning while ensuring that adjacent tuning intervals overlap each other, which avoiding tuning blind areas caused by process errors; finally, the circuit of the third-order loop filter and the improved differential charge pump are designed. Simulation result shows that the PLL has a wideband tuning range of 19.6-27.8 GHz, the overall power consumption is 30 mW, and the phase noise at the output frequency deviation of 1 MHz is –95.6 dBc/Hz. Compared with the phase-locked loops of other literatures, the phase-locked loops designed in this paper are advanced in the tuning range under the premise that other indicators are equivalent, and can be used as a high-performance clock signal.
Keywords: microelectronics and solid-state electronics;phase locked loop;frequency divider;phase noise
2020, 46(8):94-100 收稿日期: 2020-04-02;收到修改稿日期: 2020-05-19
基金项目: 国家科技重大专项(2016ZX03001002)
作者简介: 朱耀辉（1994-），男，四川资阳市人，硕士研究生，专业方向为数模混合集成电路设计
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